发明名称 |
Frequency calibration loop circuit |
摘要 |
A frequency calibration loop circuit having a pre-set frequency channel word (FCW) command value, a bit inputted to obtain a target frequency in an oscillator and a pre-set minimum division ratio n (n is a constant) of a programmable divider, includes: an oscillator adjusting an oscillation frequency of an oscillation signal according to a control value; a programmable divider dividing the oscillation signal according to a division ratio to output a divided signal; a counter counting the number of clocks of the divided signal for one cycle of a reference signal to output a count value; and a frequency detector obtaining the control value by subtracting the count value from a reference comparison value, wherein the reference comparison value is obtained by dividing a Frequency Channel Word (FCW) command value by a minimum division ratio of the programmable divider.
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申请公布号 |
US8031009(B2) |
申请公布日期 |
2011.10.04 |
申请号 |
US20090581105 |
申请日期 |
2009.10.16 |
申请人 |
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE |
发明人 |
MIN BYUNG HUN;LEE JA YOL;KIM SEONG DO;KIM CHEON SOO;YU HYUN KYU |
分类号 |
H03L7/085;H03L7/081;H03L7/095;H03L7/18 |
主分类号 |
H03L7/085 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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