发明名称 |
Minimizing non-linearity errors |
摘要 |
A system and method for minimizing non-linearity errors induced in output drive voltage of a transmitter circuit due to on-chip process, voltage, and temperature (PVT) variations. The system including an oscillator for converting an input reference bias voltage into a clock output signal, where the input reference bias voltage varies in response to PVT variations. Also included is a counter for counting the clock output signal and generating a count value corresponding to the clock output of the oscillator. A comparison module operatively coupled to the counter compares the count value with a pre-simulated count value to generate an error signal. Based on the error signal generated by the comparison module, a correction logic adjusts an output drive signal of the transmitter circuit making it immune to PVT variations.
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申请公布号 |
US8004345(B2) |
申请公布日期 |
2011.08.23 |
申请号 |
US20090491514 |
申请日期 |
2009.06.25 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
RAMAMOORTHY NAVIN KUMAR;SHUKLA UMESH K;REDDY K. S. SANKARA |
分类号 |
H01L35/00;H01L37/00;H03K3/42;H03K17/78 |
主分类号 |
H01L35/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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