发明名称 VERIFICATION COMPUTER PRODUCT, METHOD, AND APPARATUS
摘要 A recording medium stores a verification program that causes a computer to execute detecting from a model circuit, a first circuit representing junction of a source region and a substrate region and including a junction resistance and a junction capacitance, a second circuit parallel to the first circuit, representing junction of a drain region and the substrate region, and including a junction resistance and a junction capacitance equivalent to the junction resistance and capacitance of the first circuit, and a connection resistance connecting the circuits and a substrate electrode; calculating, using the junction resistances and connection resistance, a first coefficient indicating impact of the junction resistances and connection resistance on amplitude variation; calculating, using the junction capacitances and connection resistance, a second coefficient indicating impact of the junction capacitances and connection resistance on phase variation; correcting the junction capacitances using a sum of the coefficients; and outputting a correction result.
申请公布号 US2011202895(A1) 申请公布日期 2011.08.18
申请号 US201113020615 申请日期 2011.02.03
申请人 FUJITSU SEMICONDUCTOR LIMITED 发明人 MIYAOKA HIROKI;YAMAGUCHI SEIICHIRO;SAKATA TSUYOSHI
分类号 G06F17/50;G06F9/455 主分类号 G06F17/50
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