发明名称 Compensation techniques for reducing power consumption in digital circuitry
摘要 A compensation circuit for reducing power consumption in at least one digital circuit includes a first sample circuit connected to a first supply voltage, a second sample circuit connected to a second supply voltage, and a controller connected to the first and second sample circuits. The first and second sample circuits are substantially functionally equivalent to one another but optimized for different regions of operation within a specified range of PVT conditions. The controller is operative to receive respective output signals from the first and second sample circuits, to monitor a functionality of the second sample circuit relative to the first sample circuit, and to adjust a level of the second supply voltage to ensure correct operation of the second sample circuit throughout the specified range of PVT conditions. The digital circuit is operative from the second supply voltage.
申请公布号 US7965133(B2) 申请公布日期 2011.06.21
申请号 US20070160373 申请日期 2007.10.31
申请人 AGERE SYSTEMS INC. 发明人 ANIDJAR JOSEPH;MOBIN MOHAMMAD S.;SHEETS GREGORY W.;SINDALOVSKY VLADIMIR;SMITH LANE A.
分类号 G05F1/10 主分类号 G05F1/10
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