| 摘要 |
PROBLEM TO BE SOLVED: To provide a latency counter in which reduction in a latch margin of the internal command due to jitter is suppressed. SOLUTION: The latency counter includes an input selecting circuit 310 that supplies an internal command to any one of signal paths La0-La7, a shift circuit 320 that switches a correspondence relation between the signal paths La0-La7 and a latch circuit 330, and an output selecting circuit 340 that causes the internal command taken in the latch circuit 330 to be output. The input selecting circuit 310 includes timing control circuits 310-0 to 310-7 allocated to each of the signal paths La0-La7, and the timing control circuits include SR latch circuits 311 that are set by the internal command and are reset in response to deactivation of a corresponding count value. Consequently, shortening of an active period of the internal command that is output from the input selecting circuit 310 is suppressed. COPYRIGHT: (C)2011,JPO&INPIT |
