发明名称 Efficient Reduction of Read Disturb Errors in NAND FLASH Memory
摘要 Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block.
申请公布号 US2011040932(A1) 申请公布日期 2011.02.17
申请号 US20100879966 申请日期 2010.09.10
申请人 TEXAS MEMORY SYSTEMS, INC. 发明人 FROST HOLLOWAY H.;CAMP CHARLES J.;FISHER TIMOTHY J.;FUXA JAMES A.;SHELTON LANCE W.
分类号 G06F12/02 主分类号 G06F12/02
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