| 摘要 |
PROBLEM TO BE SOLVED: To provide a layout verification method and a layout verification device capable of reducing the layout data generation time. SOLUTION: The layout verification device extracts data required for layout verification 21 from semiconductor layout data 20, excluding the internal pattern of a macro cell. The layout verification device adds frame GDS information data 23 on data relating to the semiconductor layout data 20 extracted. Then, the layout verification device performs layout verification 21, on the data relating to the semiconductor layout data 20 with the frame GDS information data 23 added thereto. COPYRIGHT: (C)2011,JPO&INPIT
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