发明名称 ANALYZING DEVICE AND ANALYZING METHOD
摘要 PROBLEM TO BE SOLVED: To reduce the amount of test pattern information. SOLUTION: A function library storage memory 212 stores calculation expressions corresponding to each of algorithms of a memory test. A FAIL information analysis part 230 obtains the test result of the memory test. An algorithm identifying part 237 identifies the algorithm of the memory test on the basis of the test result obtained by the FAIL information analysis part 230. A calculation expression selection part 238 selects a calculation expression corresponding to the algorithm identified by the algorithm identifying part 237 among the calculation expressions stored by the function library storage memory 212. A calculation processing part 240 creates a fail bit map on the basis of the test result and the calculation expression selected by the calculation expression selection part 238. The calculation processing part 240 outputs the created fail bit map. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2010272149(A) 申请公布日期 2010.12.02
申请号 JP20090120956 申请日期 2009.05.19
申请人 FUJITSU SEMICONDUCTOR LTD 发明人 KATO DAIICHIRO;HIRAMATSU TETSUYA
分类号 G11C29/44 主分类号 G11C29/44
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