发明名称 |
Method to identify timing violations outside of manufacturing specification limits |
摘要 |
A method of evaluating an integrated circuit design selects manufacturing parameters of interest which are outside of manufacturing specification limits. Then, the method runs timing tests on the integrated circuit design and successively evaluates the timing test results in an iterative process that considers the timing performance sensitivity to the selected manufacturing parameters of interest. The design is made more robust to each parameter out of manufacturing range.
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申请公布号 |
US7844932(B2) |
申请公布日期 |
2010.11.30 |
申请号 |
US20080045915 |
申请日期 |
2008.03.11 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BUCK NATHAN C.;DUBUQUE JOHN P.;FOREMAN ERIC A.;HABITZ PETER A.;VISWESWARIAH CHANDRAMOULI |
分类号 |
G06F17/50;G06F9/45 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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