摘要 |
<p>The present invention relates to, a method for assigning a target (CSG) to a configurable oscillator (VCO) of a phase-locked loop (PLL), the phase-locked loop (PLL) receiving samples (PCRr, PCR1r, PCR2r) of a first signal realised according to a sampling clock (CLKech) and producing local samples (PCR_Loc, PCR_Loc1, PCR_Loc2) of a second signal, said phase-locked loop (PLL) also producing the second signal from a reconstituted clock (CLK_out) delivered by the configurable oscillator (VCO), the target (CSG) of the phase-locked loop (PLL) having by default a value equal to CSGinit. According to the invention, at the start-up of said phase-locked loop (PLL), it comprises: - a step (10) to memorise a value of a sample (PCR1r) received and a local sample value (PCR_Loc1) produced at a time t1 where the sample (PCR1r) is valid and the value of the target (CSG) is set at a value CSGinit, - a step (20) to memorise a sample value (PCR2r) received following the sample (PCR1r) and a local sample value (PCR_Loc2) produced at a time t2 where the sample (PCR2r) is valid and the value of the target (CSG) is set at the value 20 CSGinit, - a step (30) to evaluate and assign a value of CSGacc = CSGinit.(PCR_Loc2 -PCR_Loc1)/(PCRr2 -PCRr1) - a step (60) to assign to an accumulation corrector (COR) of the phase-locked loop (PLL) an initialisation value COR INIT the value CSG acc and to assign to the target (CSG) a corrected difference (ERC) delivered by the accumulation corrector (COR) in response to a difference (ERR) between a received sample (PCRr) and a local sample (PCR_Loc).</p> |
申请人 |
THOMSON LICENSING;DEFRANCE, SERGE;JOLLY, EMMANUEL;TAPIE, THIERRY |
发明人 |
DEFRANCE, SERGE;JOLLY, EMMANUEL;TAPIE, THIERRY |