| 摘要 |
<P>PROBLEM TO BE SOLVED: To surely receive data from a DQ signal according to the rising and falling of a DQS signal. Ž<P>SOLUTION: A memory control device 2 includes: a receiver circuit 20 which delays a DQS signal whose rising edge and falling edge appear in a fixed cycle, and generates a plurality of delay DQS signals having delay times different from each other; a data extraction part 210 for extracting the data of a section corresponding to the rising edge or falling edge of the generated delay DQS signal from a DQ signal partially having already known reference data; a data determination part 240 for determining whether or not the extracted data are matched with reference data; and an upper and lower limit value determination part 250 for determining the range of the delay time corresponding to the rising edge of the DQS signal and the range of the delay time corresponding to the falling edge of the DQS signal from the delay time of the delay DQS signal corresponding to the data determined to coincide. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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