| 摘要 |
An embodiment of an embedded cache memory in an image sensor comprises a memory cell array wherein the memory cells are substantially isolated from laterally adjacent memory. The memory cell array includes a plurality of memory cells. Each of the memory cells is formed in a standard CMOS image sensor process without the need for SOI processes. Each cell includes first and second n-type and p-type regions arranged around a vertically integrated gate. Data is written to a cell by causing carriers to accumulate in the body of the device through carrier generation mechanisms that may include impact ionization, band-to-band tunneling and/or channel-initiated secondary hot electrons.
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