| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory controller and a data processor for grouping requests from a plurality of memory access requesters in order to increase the use efficiency of a bus. SOLUTION: A request queue 22 stores requests received from a plurality of memory access requesters. A merge section 31 merges requests accessible in one read cycle or write cycle in a DDR2-SDRAM among requests in the request queue 22. A memory interface part 27 accesses the DDR2-SDRAM according to the requests, and accesses the DDR2-SDRAM in response to the merged requests in a batch. COPYRIGHT: (C)2010,JPO&INPIT |
