| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a reference voltage generating circuit and bias circuit, for suppressing gain variation caused by process variation. Ž<P>SOLUTION: F1-F3 are depression-mode FETs, Tr1-Tr4 are HBTs, R1-R6 are resistors, Vcb is a power supply terminal, Ven is an enable terminal, and Vref is a reference voltage terminal. A threshold voltage compensation circuit includes F3, R5, R6, Tr4. In the case where a threshold voltage Vth of the depression-mode FET is deep, a drawing current I1 of the threshold voltage compensation circuit is increased. Hence, currents flowing in Tr1 and R3 are decreased, which suppresses voltage elevation at a collector end of Tr1. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
|
