| 摘要 |
<P>PROBLEM TO BE SOLVED: To obtain a divider circuitry for a phase-locked loop frequency synthesizer for use of a radio communication system generating a desired and stable carrier signal. <P>SOLUTION: The divider circuitry for the phase-locked loop frequency synthesizer comprises a main divider configured to divide an input signal received from a feedback path of the phase-locked loop frequency synthesizer by a division ratio selected from a pair of dual modulus division ratios in accordance with a dual modulus selection signal; and an auxiliary divider comprising a shift register clocked by an output signal of the main divider, the shift register comprising a parallel input configured to receive parallel input data in the form of a fraction selection signal at the start of a cycle, and a serial output connected to a control input of the main divider, the auxiliary divider being configured to produce a pulse once per cycle and to output the pulse to a phase detector. <P>COPYRIGHT: (C)2010,JPO&INPIT |
