Architecture for computer in e.g. Ethernet, has circuit disconnecting communication of all ports managed by switch-matrix based on detection of error function of one of ports and sending error message to preset destination address

摘要

The architecture has a circuit e.g. field programmable gate array (FPGA) and application specific integrated circuit (ASIC), provided parallel to a switch-matrix i.e. microchip, of a communication device i.e. computer, where ports are managed by the switch-matrix. The circuit detects an error function of one of the ports, and disconnects communication of all the ports managed by the switch-matrix based on the detection of the error function. The circuit sends an error message to a preset destination address i.e. media access control (MAC) address.