IMPLEMENTING VARIATION TOLERANT MEMORY ARRAY SIGNAL TIMING

摘要

PURPOSE: A method, a circuit thereof, and a design structure thereof are provided to offer variation allowable memory array signal timing by implementing a logic delay circuit which is programmed by a control signal. CONSTITUTION: A logic circuit(102) forms logic devices. The logic circuit receives a set delay signal. The logic circuit generates a first delay signal based on the logic devices. A memory cell circuit(106) receives a first delay signal. A memory cell circuit generates control signals based on memory cell devices forming a memory cell circuit. A programmable logic delay circuit(108) generates a timing adjustment signal.