发明名称 PHASING SIMULATOR AND WIRELESS COMMUNICATION DEVICE TEST SYSTEM
摘要 <P>PROBLEM TO BE SOLVED: To reduce a possibility to perform an erroneous measurement by enabling a state of clipping processing at a phasing simulator to be easily recognized. <P>SOLUTION: The phasing simulator 30 includes: a phasing processing section 31 for applying desired phasing processing to an input data signal Da and outputting a data signal Db subjected to the phasing processing with M digits more than the number N of digits of a D/A converter 23; a clip processing section 33 for performing clip processing onto the output data signal Db of the phasing processing section 31 with a specific value indicated by the N digits as an upper limit value and outputting a data signal obtained by the clip processing; a clip frequency detection section 35 for obtaining a frequency of data on which clip processing has been performed by the clip processing section 33; and a display section 45 for displaying a detection result of the clip frequency detection section 35. <P>COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010098650(A) 申请公布日期 2010.04.30
申请号 JP20080269583 申请日期 2008.10.20
申请人 ANRITSU CORP 发明人 YAMADA YASUNORI;MATSUO TOMOKO
分类号 H04B17/00 主分类号 H04B17/00
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