| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a controller capable of preventing malfunction due to a deviation between initialization processing completion timing of a rewritable device such as an FPGA and reset cancel timing of a control unit. <P>SOLUTION: When a main switch SW1 is turned on, a battery power supply voltage BATT is supplied to an FPGA 2 and a power supply monitor IC 5, and the FPGA 2 reads configuration information out of a configuration ROM 3 and starts initialization processing. When an ignition switch signal IGSW is input to a main relay circuit 6, Meanwhile, the power supply monitor IC 5 supplies a supply voltage Vcc to a CPU 1 and also outputs a reset cancel signal RESET to an AND circuit 8 a certain time later, and after the FPGA2 outputs a configuration completion signal, the AND circuit 8 inputs an ON signal to a reset cancel signal input terminal of the CPU 1. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
