| 摘要 |
<p>An input signal having a binary waveform is reproduced at high speed and low power consumption. A clock reproduction circuit is provided with an equalizing circuit for equalizing the input signal having the binary waveform to a duo-binary signal, determining the level of the duo-binary signal with respect to a plurality of thresholds at the timing of a symbol rate clock signal, and outputting the result of the determination, a phase comparison circuit for outputting the result of phase comparison indicating the phase shift of the symbol rate clock signal according to the result of the determination, and a phase adjustment circuit for increasing or decreasing the period of the symbol rate clock signal according to the result of the phase comparison.</p> |
