| 摘要 |
A data decoder device operable to perform interleaved decoding operations. The device has an array of decoder units (5A-5P) operable to provide a selectable number of decoder units for use in parallel, has RAM addresses in RAM units (6A-6P) and has an interconnect (7,8) operable to provide interconnection between the decoder units and the RAM addresses. Interconnection addresses are provided by an addressing unit. The addressing unit is operable to perform barrel shift operations on a data set representing decoder units relative to datasets representing RAM addresses to provide updated interconnection addresses, thereby avoiding RAM contention when performing decoding. In a specific embodiment the device is operable to perform turbo decoding. |
