| 摘要 |
Provided are a clock regeneration circuit and a receiver, in which difference values (V1, V2, V3) from an ideal value can be obtained with respect to three sets of sample data (T1, T2, T3) including sample data (T2) at a symbol point (P) in the center and obtained by oversampling a quadrature FSK demodulated signal at a higher frequency than that of a symbol clock, respectively, and the sampling timing of the symbol point (P) is moved by the time corresponding to the difference value (V2) at the symbol point in the direction in which the sample data (T3) with a small difference value was obtained. Thus, the clock regeneration circuit and the receiver are capable of regenerating a stable clock from multilevel modulated waves with a small amount of calculation. |
