发明名称 METHOD OF FABRICATING WAFER LEVEL PACKAGE
摘要 PURPOSE: A method for manufacturing a wafer level package is provided to prevent a crack in a joint of a solder ball by minimizing stress applied to the solder ball due to the thermal expansion coefficient difference. CONSTITUTION: An insulation pattern(106) covering at least two edges of each semiconductor chip is formed on an upper side of a wafer. The upper side of the wafer includes a plurality of semiconductor chips(102) divided with a scribe line(104). An external connection terminal is attached to each semiconductor chip of the wafer including the semiconductor chips with the insulation pattern. The wafer including each semiconductor chips with the external connection terminal is sawn to the individual semiconductor chip along the scribe line.
申请公布号 KR20100002867(A) 申请公布日期 2010.01.07
申请号 KR20080062916 申请日期 2008.06.30
申请人 HYNIX SEMICONDUCTOR INC. 发明人 KIM, JAE MYUN;CHUNG, QWAN HO
分类号 H01L23/12;H01L21/78 主分类号 H01L23/12
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