SEMICONDUCTOR DEVICE REDUCING OUTPUT CAPACITANCE DUE TO PARASITIC CAPACITANCE

摘要

PURPOSE: A semiconductor device reducing output capacitance due to parasitic capacitance is provided to reduce the output capacitance of a SOI(Silicon On Insulator) LDMOSFET(Lateral Double Diffused MOSFET) by maintaining the durability of the semiconductor substrate. CONSTITUTION: An insulation layer(2) is formed on a surface of a semiconductor substrate(1). An N type semiconductor layer(3) is formed on the surface of the insulation layer. An N+ drain region(4) is formed on the N type semiconductor layer. A P type well region(5) is formed from the surface of the N type semiconductor layer to the insulation layer. The N+ source region(6) is formed on the P type well region. A P+ body contact region(7) is formed on the N+ source region. A drain electrode(9) is formed on the surface of the N type semiconductor layer by an insulation film(8). A source electrode(11) is formed on the surface of the P type well region by the insulation film. A gate electrode(12) is formed on the surface of the P type well region between the N+ drain region and the N+ source region.