| 摘要 |
PURPOSE:To execute the highly speedy data transfer without passing through the processor by providing a transfer data block length designating means, etc., dividing the transfer data to the block of the optional data length and inserting the dummy data between blocks. CONSTITUTION:When the data are transferred through a bus 1 from a peripheral device to a memory, first, the trigger of the transfer start to a control circuit 10 is indicated, thereby the transfer is started. Next, the block length of the transfer data is designated through a data signal line 101 by a register 16, the transfer length of the dummy data is designated by a register 17, and inputted through signal lines 160 and 170 to a selecting circuit 18. The circuit 18 selects either of the lines 160 and 170, the output is inputted through a register 20 to a subtracter circuit 21, and when the contents of the register 20 go to be zero, the output is sent through a signal line 211 to the circuit 10. Thus, the transfer of the data block and the dummy data is interchangeably executed and the highly speedy data transmission can be executed without passing through the processor.
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