发明名称 Buffer circuit with reduced power consumption
摘要 A buffer circuit is provided, having an odd number of stages of inverting amplifiers, wherein the stages are capacitive coupled. A negative feedback path feeds back from an output terminal of the final stage of the inverting amplifiers to an input terminal of the initial stage. A reference current source is also provided. A first switch is provided between the adjacent stages of the inverting amplifiers and switched, depending upon a mode of operation. A second switch is provided for selectively driving at least a transistor(s) in the final stage to cause a current mirror circuit with the reference current source depending upon a mode of operation.
申请公布号 US7626428(B2) 申请公布日期 2009.12.01
申请号 US20060921823 申请日期 2006.06.08
申请人 TPO HONG KONG HOLDING LIMITED 发明人 MATSUKI FUMIROU
分类号 H03K3/00 主分类号 H03K3/00
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