| 摘要 |
PROBLEM TO BE SOLVED: To provide a latency counter capable of increasing signal quality of outputting an internal command. SOLUTION: The latency counter includes a point shift type FIFO circuit 300 to be controlled with a count value of a counter circuit 200. The point shift type FIFO circuit 300 includes: a wired OR circuit 351 for synthesizing outputs of latch circuits 330-0 to 330-3; a wired OR circuit 352 for synthesizing outputs of latch circuits 330-4 to 330-7; a gate circuit 353 for synthesizing outputs of the wired OR circuits 351, 352; and reset circuits 354, 355 for respectively resetting the wired OR circuits 351, 352 on the basis of the count value of the counter circuit 200. The high signal quality can be obtained since an output load is decreased as compared with such a case that the outputs of all latch circuits are made to be wired-OR connected. COPYRIGHT: (C)2010,JPO&INPIT |
