发明名称 SYSTEM FOR PROVIDING TRACE DATA IN A DATA PROCESSOR HAVING A PIPELINED ARCHITECTURE
摘要 The invention is a method and system for providing trace data in a pipelined data processor. Aspects of the invention include providing a trace pipeline in parallel to the execution pipeline, providing trace information on whether conditional instructions complete or not, providing trace information on the interrupt status of the processor, replacing instructions in the processor with functionally equivalent instructions that also produce trace information and modifying the scheduling of instructions in the processor based on the occupancy of a trace output buffer.
申请公布号 WO2009133354(A2) 申请公布日期 2009.11.05
申请号 WO2009GB01070 申请日期 2009.04.28
申请人 IMAGINATION TECHNOLOGIES LIMITED;ISHERWOOD, ROBERT, GRAHAM;OLIVER, IAN;WEBBER, ANDREW 发明人 ISHERWOOD, ROBERT, GRAHAM;OLIVER, IAN;WEBBER, ANDREW
分类号 G06F9/38 主分类号 G06F9/38
代理机构 代理人
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