| 摘要 |
<P>PROBLEM TO BE SOLVED: To evade high voltage stress relating to breakdown phenomenon during erasing data. <P>SOLUTION: In the semiconductor memory device and method, a flash memory cell array fabricated in a well is included together with memory cells in the same column connected to each other in series and connected to respective bit lines. The memory devices also include a column decoder, a data register buffer unit, a row decoder, an erase control unit, and an input/output buffer unit. In one or more embodiments, the erase control unit applies voltage to the well to erase the memory cells in a manner that breaking down of p-n junction formed by transistors fabricated in the well is avoided. In another embodiment, high voltage transistors are used to selectively isolate the bit lines from and couple the bit lines to a peripheral circuit in pairs so that each high voltage transistor is shared by two bit lines. <P>COPYRIGHT: (C)2009,JPO&INPIT |
