| 摘要 |
A recording apparatus detects a preamble, which is a series of patterns formed on a track, and generates a clock based on the preamble. The recording apparatus then detects a Sync mark, which is a predetermined pattern formed between the preamble and a Resync mark, calculates a predicted position of the next Resync, and switches PLL gain to a low level. The recording apparatus then detects the Resync mark, which is a pattern of equal to or more than one pulse, and corrects the generated clock. Specifically, upon detecting the Resync mark, the recording apparatus compares a timing of the predicted position of the Resync, and the timing at which the Resync mark is actually detected to correct a write clock.
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