发明名称 METHOD AND SYSTEM FOR CREATING A BOOLEAN MODEL OF MULTI-PATH AND MULTI-STRENGTH SIGNALS FOR VERIFICATION
摘要 A system, method, computer program product for verification and equivalence checking. In one approach, the system, method, and computer program product analyzes the switching paths in a manner consistent with circuit functionality to provide a complete application which can verify the complex characteristics in the circuits to the accurate RTL model function, including FPGA, ROM Arrays, RAM circuits, and other custom integrated circuit designs.
申请公布号 US2009113363(A1) 申请公布日期 2009.04.30
申请号 US20080260353 申请日期 2008.10.29
申请人 CADENCE DESIGN SYSTEMS, INC. 发明人 KHOO KEI-YONG;HINES MITCHELL;LIN CHI-CHANG
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址
您可能感兴趣的专利