发明名称 Verfahren zur UEberwachung des synchronen Laufes zweier identischer binaerer Schaltaggregate
摘要 <p>915,776. Comparing digital data. SOC. TECHNIQUE POUR L'INDUSTRIE NOUVELLE S.A. March 21, 1961 [March 22, 1960], No. 10200/61. Class 106 (1). Apparatus for continuously comparing the contents of two identical binary registers comprises for each pair of stages first and second " or " gates, the first " or " gate of each pair of stages being connected to the direct output of one stage and the inverse output of the other stage, the second " or " gate being connected to the inverse output of the first stage and the direct output of the second stage, the outputs of all the first " or " gates being arithmetically added to produce a first total and the outputs of all the second " or " gates being added arithmetically to produce a second total, the first and second totals being compared with each other or added together and compared with a predetermined constant quantity. As described, two n-stage registers A, B are compared. For each pair of stages A i , Bi, a i and #b i are connected to a gate G i and #a i and b i to a gate G<SP>1</SP>i. The outputs of the gates G i are connected together to produce an output current representing and the outputs of the gates G<SP>1</SP> i are connected together to produce an output current representing The currents I and I<SP>1</SP> are supplied to coils L 1 , L 2 of a transductor, the fluxes in the coils balancing if the two currents are equal which is the case when each stage A i is in the same stage as B i . If each stage A i is not in the same state as B i , the currents I, I<SP>1</SP> may or may not be equal. To make a complete comparison, the currents I, I<SP>1</SP> are added in a further coil L 3 which is one winding of a further transductor, the other coil L 4 of which carries a current proportional to 2n. If the two currents in L 3 , L 4 are equal, then each stage A i is in the same state as B i . If the currents are unequal, that at least one pair of corresponding stages differ. The output of the gates may alternatively be voltages rather than currents, these voltages being applied to a differential amplifier to effect the required comparison.</p>
申请公布号 DE1136142(B) 申请公布日期 1962.09.06
申请号 DE1961S072909 申请日期 1961.03.09
申请人 SOCIETE TECHNIQUE POUR L'INDUSTRIE NOUVELLE S. A. IASTINIA 发明人
分类号 B61L1/20;F16D65/54;G06F7/02;G06F11/16 主分类号 B61L1/20
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