| 摘要 |
A delay-locked loop (DLL) includes a delay line and a control circuit. The delay line delays an input clock signal based on at least one phase control signal to generate an output clock signal. The at least one phase control signal indicates whether the output clock signal leads or lags the input clock signal. The control circuit generates a division control signal by determining whether the output clock signal is locked with respect to the input clock signal, and generates the at least one phase control signal based on the division control signal. Accordingly, a locking time and bang-bang jitter may be reduced.
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