| 摘要 |
PROBLEM TO BE SOLVED: To prevent an increase in design/verification TAT of a semiconductor integrated circuit in full consideration of the pattern dependency of transistor characteristics. SOLUTION: This design method for a semiconductor integrated circuit includes steps of: (A) creating a delay library for statistical STA; (B) creating layout data; and (C) calculating the delay value of an object cell. The statistical STA delay library provides a delay function expressing a cell delay value as the function of the model parameter of a transistor in the cell. The step (C) includes steps of: (C1) extracting a parameter for defining the layout pattern around an object transistor in the object cell; (C2) modulating the model parameter of the object transistor; (C3) calculating the reference delay value of the object cell by using the delay function; (C4) calculating delay fluctuation from the reference delay value corresponding to the modulation quantity of the model parameter by using the modulation quantity of the model parameter and the delay function in the step (C2). COPYRIGHT: (C)2009,JPO&INPIT
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