发明名称 |
Parallel test mode for multi-core processors |
摘要 |
An embodiment of the present invention is a technique to provide a parallel test mode for multi-core processors. A test access port (TAP) in a first processor core generates a first test data output (TDO) from a first test data input (TDI) or a first delayed TDI according to a TDO select bit. The first delayed TDI is clocked by a test clock (TCK). The first processor core has a first core circuit. The TAP generates a phase select word. A clock generator generates a clock signal synchronized with the TCK and has a low phase and a high phase. A first enable circuit enables first core data from the first core circuit in one of the low and high phases of the clock signal according to the phase select word.
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申请公布号 |
US7475309(B2) |
申请公布日期 |
2009.01.06 |
申请号 |
US20050174198 |
申请日期 |
2005.06.30 |
申请人 |
INTEL CORPORATION |
发明人 |
PICANO SILVIO;JAYARAMAN SRIDHAR;DESROSIER PETER;CHUNG JAMES |
分类号 |
G01R31/28 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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