发明名称 BUFFER CIRCUIT OF COMPLEMENTARY INSULATED GATE FIELD EFFECT TRANSISTOR
摘要 PURPOSE:To reduce the voltage consumption, by making the first and the second insulated FETs conductive and non-conductive respectively by complementary input signals and by operating the third and the fourth insulated FETs between a prescribed power source voltage and the earth voltage. CONSTITUTION:When complementary input signals of -V and 0 are applied to gate electrodes of FETs MP2 and MP3 FETs MP2 and MP3 become comductive and non-conductive respectively. When the FET MP2 becomes conductive, electric charge of a capacity C1 is discharged, and a capacity C4 is charged, and as the result, the output of the first inverter circuit consisting of FETs MP2 and Mn2 and a resistance R1 approaches 0. Then, an FET Mn3 becomes conductive, and a capacity C3 is discharged, and a capacity C2 is charged, and the output of the second inverter circuit consisting of FETs MP3 and Mn3 and a resistance R2 approaches a voltage -V2. Next, when complementary input signals of 0 and -V1 are applied to gate electrodes of FETs MP2 and MP3, the operation opposite to above is performed. Thus, a buffer circuit - is operated.
申请公布号 JPS5778227(A) 申请公布日期 1982.05.15
申请号 JP19810142327 申请日期 1981.09.11
申请人 HITACHI SEISAKUSHO KK 发明人 FUJITA MINORU
分类号 H03K3/353;H01L21/8238;H01L27/092;H01L29/78;H03K5/02;H03K19/0185 主分类号 H03K3/353
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