发明名称 QUEUE STRUCTURE FOR DATA PROCESSOR
摘要 PURPOSE:To improve the interrupt responsiveness by providing a pointer and a level storage place for an intermediate frame in a control frame of the queue structure and making it possible to restart the processing from the interruption point of an instruction which is interrupted with an external interrupt. CONSTITUTION:A common control frame 31 controls priority frames 36 and 40 in a queue and has four element. The first and the last frame pointers 32 and 33 indicate the first and the last frames of priority in the queue, and an intermediate frame pointer 34 indicates a frame where an instruction is interrupted with an interrupt, and the program level at this interruption time is stored in an area 35. By the adding instruction of a new frame, contents of a priority memory 37 in the frame 36 are read out successively and are compared with the additional frame, and the position of this frame where the frame should be placed in the queue is determined. Thus, the execution of instructions is restarted from the interruption point in the frame which is interrupted with the interruption of the additional frame, and the interrupt responsiveness is improved, and low-level queue instructions are executed efficiently.
申请公布号 JPS59189452(A) 申请公布日期 1984.10.27
申请号 JP19830064079 申请日期 1983.04.12
申请人 NIPPON DENKI KK 发明人 SATOU HIROSHI;MORITA NOBUTERU
分类号 G06F9/46 主分类号 G06F9/46
代理机构 代理人
主权项
地址