| 摘要 |
PURPOSE:To simplify a data transfer process between data buses whose word lengths are different by separately deciding the number of addresses which simultaneously specifies a memory concerning data input and data output respectively. CONSTITUTION:The variable range of the word length is set as 8, 16 and 32 in both inputs and outputs, the least common multiple in the variable range is set as 32 and the capacity of the memory 1 is the multiple of 32. Therefore, even if the input has any word length, it does not cause an odd space where the input is impossible in a memory space. Namely, the accumulation of the data quantity, inputted or outputted, has nodes every 32 bits. Since the variable range of the word length is the multiple of 8, addressing is simplified by dividing every data of 8 bits. The memory 1 can separately specify the address for input and the address for output.
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