| 摘要 |
The digital equalizer is deposited prior to a filter to modulate pulse width of digital pulse data which is transmitted to a filter so that jitter and inter-symbol-interference of digital pulse data are minimized. The digital equalizer comprises a time delaying circuit (10) comprising n-number of delayers to generate n- number of delayed data, a discriminator (20) for generating level selection signal according to logic state of n-number of delayed data, a voltage level adjuster (30) for generating m- number of logic level signal using m-number of voltage adder and subtractor, a transfering circuit (40) for generating logic level according to output signal of the discriminator (20).
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