发明名称 Single stage cyclic analog to digital converter with variable resolution
摘要 A converter ( 200 ) adapted to convert an analog input signal into a digital output signal includes an analog input terminal ( 205 ) for receiving the analog input signal, a Redundant Signed Digit (RSD) stage ( 210 ) coupled to the analog input terminal, and a digital section ( 220 ). The RSD stage is configured to receive the analog input signal at the analog input terminal, produce a first number of bits at a digital output from the analog input signal during a first half of a first clock cycle, provide a residual feedback signal of the analog input signal at the analog input terminal during a second half of the first clock cycle, and produce a second number of bits at the digital output from the residual feedback signal during a first half of a second clock cycle, the second number of bits less than the first number of bits.
申请公布号 US7443333(B2) 申请公布日期 2008.10.28
申请号 US20070674435 申请日期 2007.02.13
申请人 FREESCALE SEMICONDUCTOR, INC. 发明人 GARRITY DOUGLAS A.;LOCASCIO DAVID R.
分类号 H03M1/34 主分类号 H03M1/34
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