发明名称 Method of Forming Vertical Contacts in Integrated Circuits
摘要 A method of forming vertical contacts in an integrated circuit that couple one or more metal lines in a given metallization level to first and second features occupying different levels in the integrated circuit comprises various processing steps. A first etch stop layer is formed overlying at least of portion of the first feature while a second etch stop layer is formed overlying at least a portion of the second feature. An ILD layer is formed overlying the first and second etch stop layers. A photolithographic mask is formed overlying the ILD layer. The photolithographic mask defines a first opening over the first feature and a second opening over the second feature. A first etch process etches a first hole in the ILD layer through the first opening in the photolithographic mask that lands on the first etch stop layer and etches a second hole in the ILD layer through the second opening that lands on the second etch stop layer. Subsequently, a second etch process further etches the first hole so that it lands on the first feature.
申请公布号 US2008164617(A1) 申请公布日期 2008.07.10
申请号 US20070619623 申请日期 2007.01.04
申请人 ASSEFA SOLOMON;GAIDIS MICHAEL C;HUMMEL JOHN P;KANAKASABAPATHY SIVANANDA K 发明人 ASSEFA SOLOMON;GAIDIS MICHAEL C.;HUMMEL JOHN P.;KANAKASABAPATHY SIVANANDA K.
分类号 H01L23/52;H01L21/4763 主分类号 H01L23/52
代理机构 代理人
主权项
地址
您可能感兴趣的专利