发明名称 Pipelining techniques for deinterlacing video information
摘要 Pipelining techniques to deinterlace video information are described. An apparatus may comprise deinterlacing logic to convert interlaced video data into deinterlaced video data using multiple processing pipelines. Each pipeline may process the interlaced video data in macroblocks. Each macroblock may comprise a set of working pixels from a current macroblock and supplemental pixels from a previous macroblock. Other embodiments are described and claimed.
申请公布号 GB2450258(A) 申请公布日期 2008.12.17
申请号 GB20080012412 申请日期 2007.03.21
申请人 INTEL CORPORATION 发明人 SATYAJIT MOHAPATRA;STEVEN TU
分类号 H04N7/01 主分类号 H04N7/01
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