发明名称 |
IC CHIP AT-FUNCTIONAL-SPEED TESTING WITH PROCESS COVERAGE EVALUATION |
摘要 |
Methods, systems and program products for evaluating an IC chip are disclosed. In one embodiment, the method includes running a statistical static timing analysis (SSTA) of a full IC chip design; creating at-functional-speed test (AFST) robust paths for an IC chip, the created robust paths representing a non-comprehensive list of AFST robust paths for the IC chip; and re-running the SSTA with the SSTA delay model setup based on the created robust paths. A process coverage is calculated for evaluation from the SSTA runnings; and a particular IC chip is evaluated based on the process coverage.
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申请公布号 |
US2008270953(A1) |
申请公布日期 |
2008.10.30 |
申请号 |
US20070741164 |
申请日期 |
2007.04.27 |
申请人 |
FOREMAN ERIC A;GRISE GARY D;HABITZ PETER A;IYENGAR VIKRAM;LACKEY DAVID E;VISWESWARIAH CHANDRAMOULI;XIONG JINJUN;ZOLOTOV VLADIMIR |
发明人 |
FOREMAN ERIC A.;GRISE GARY D.;HABITZ PETER A.;IYENGAR VIKRAM;LACKEY DAVID E.;VISWESWARIAH CHANDRAMOULI;XIONG JINJUN;ZOLOTOV VLADIMIR |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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地址 |
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