发明名称 SILICIDE FORMATION FOR eSiGe USING SPACER OVERLAPPING eSiGe AND SILICON CHANNEL INTERFACE AND RELATED PFET
摘要 Methods of forming a suicide in an embedded silicon germanium (eSiGe) source/drain region using a suicide prevention spacer overlapping an interface between the eSiGe and the silicon channel, and a related PFET with an eSiGe source/drain region and a compressive stress liner in close proximity to a silicon channel thereof, are disclosed. In one embodiment, a method includes providing a gate having a nitrogen-containing spacer adjacent thereto and an epitaxially grown silicon germanium (eSiGe) region adjacent to a silicon channel of the gate; removing the nitrogen-containing spacer that does not extend over the interface between the eSiGe source/drain region and the silicon channel; forming a single silicide prevention spacer about the gate, the single silicide prevention spacer overlapping the interface; and forming the silicide in the eSiGe source/drain region using the single silicide prevention spacer to prevent the silicide from forming in at least an extension area of the silicon channel.
申请公布号 US2008246056(A1) 申请公布日期 2008.10.09
申请号 US20070697806 申请日期 2007.04.09
申请人 CHAN VICTOR W C;DYER THOMAS W;FANG SUNFEI;LI JINGHONG;TANG TECK J;UTOMO HENRY K;YAN JIANG 发明人 CHAN VICTOR W. C.;DYER THOMAS W.;FANG SUNFEI;LI JINGHONG;TANG TECK J.;UTOMO HENRY K.;YAN JIANG
分类号 H01L29/778;H01L21/336 主分类号 H01L29/778
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