发明名称 |
SYSTEM AND METHOD FOR DESIGNING A LOW LEAKAGE MONOTONIC CMOS LOGIC CIRCUIT |
摘要 |
A computer system for designing a low leakage monotonic CMOS logic circuit. The system performing the computer implements steps of: (a) specifying a reference PFET having its threshold voltage and its gate dielectric thickness and a reference NFET having its threshold voltage and its gate dielectric thickness; (b) synthesizing a schematic circuit design with standard design elements, the standard design elements including one or more reference PFETS and one or more reference NFETs; (c) analyzing one or more circuits for logic stages having predominantly high input logic states or predominantly low input logic states; (d) selecting one or more logic stages determined to have predominantly high input logic states or predominantly low input logic states; and (e) replacing the standard design elements of the selected logic stages with reduced current leakage elements.
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申请公布号 |
US2008195987(A1) |
申请公布日期 |
2008.08.14 |
申请号 |
US20080103038 |
申请日期 |
2008.04.15 |
申请人 |
BERNSTEIN KERRY;ROHRER NORMAN J |
发明人 |
BERNSTEIN KERRY;ROHRER NORMAN J. |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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