| 摘要 |
In order to obtain substantially identical operation speed of a p-type MOS transistor and n-type MOS transistor constituting the CMOS circuit, the n-type MOS transistor has a three-dimensional structure having channel regions on both of the (100) surface and the (110) surface and the p-type MOS transistor has a planer structure having a channel region only on the (110) surface. Furthermore, the circuit is configured so that the areas of the channel regions and the gate insulation films of the both transistors are identical to each other. Thus, it is possible to obtain identical area of the gate insulation film and the like and the gate capacity. |
