| 摘要 |
A memory controller includes a phase locked loop (PLL) to generate a differential reference clock and a first clocking component coupled to the PLL. The first clocking component includes a first delay locked loop (DLL) to receive the reference clock and to generate de-skewed transmit and receive clock signals, a first set of phase interpolators to provide de-skewed transmit data, and a first set of slave delay lines to provide received data de-skewing. Keyword: skew. |
