| 摘要 |
A system, a method, and a device for pre-fetching data from a DRAM to an SRAM are provided to offer memory resources suitable for CMP(Chip Multi-Processor) scaling by transferring more than two cache lines from an open page of the DRM to the SRAM. A core logic unit(302-1 to 302-n) provides a pre-fetch hint for pointing a confidence level related to transfer of more than two cache lines. A pre-fetch logic unit(404) is connected to the core logic unit. The pre-fetch logic transfers more than two cache lines from an open page of a DRAM(312) to an SRAM based on the pre-fetch hint through a high density interface such as a die-to-die via or a through-silicon via. The DRAM provides an L(layer)3 cache(310) and the SRAM provides an L2 cache(402). |
