| 摘要 |
A phase selector is disclosed. The phase selector is utilized for outputting an output clock to a flip-flop according to an input data signal latched by the flip-flop. The phase selector includes: a clock phase adjustor, for adjusting the delay of an input clock to generate a first clock and a second clock, wherein the clock phases of the first clock and the second clock are different; a phase detector, for detecting phase relation between the input data signal and the first clock to generate a detecting signal; a decision circuit, coupled to the phase detector, for generating a selecting signal according to the detecting signal; and a selection circuit, coupled to the decision circuit, for selecting the input clock or the second clock to generate the output clock to the flip-flop according to the selecting signal. |
