发明名称 CALIBRATION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a calibration circuit which is capable of carrying out sufficient calibration operation even in the case where the frequency of an external clock is high. SOLUTION: The calibration circuit comprises: a first replica buffer 110 including the substantially same circuit configuration as a pull-up circuit constituting an output buffer; and a second replica buffer 130 including the substantially same circuit configuration as a pull-down circuit constituting the output buffer. When a first calibration command ZQCS is issued, both of control signals ACT1, ACT2 are activated to simultaneously perform calibration operations on the first and second replica buffers 110, 130. When a second calibration command ZQCL is issued, the control signals ACT1, ACT2 are alternately activated to alternately perform calibration operations on the first and second replica buffers 110, 130. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008135925(A) 申请公布日期 2008.06.12
申请号 JP20060319937 申请日期 2006.11.28
申请人 ELPIDA MEMORY INC 发明人 YOKO HIDEYUKI
分类号 H03K19/0175;H01L21/822;H01L27/04;H03K19/0948 主分类号 H03K19/0175
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